Among the persistent trends in the field of integrated semiconductor devices is the trend towards smaller and smaller devices. Device size is conventionally defined in terms of a "design rule", typically equivalent to the smallest planar device dimension. Current design rules in some commercially available Si-based integrated circuits (ICs) are below 1 .mu.m (e.g., 0.9 .mu.m), with further reduction being a virtual certainty. In the context of field effect transistors (e.g., CMOS technology), the smallest planar device dimension typically is the channel length.
Reduction of the channel length substantially below 1 .mu.m (e.g., below about 0.5 .mu.m) will require the fabrication of substantially more shallow source and drain junctions than are currently used, in order to avoid, inter alia, punch-through and short channel effects. Conventional contact metalization of such ultra-shallow (typically .ltoreq.100 nm) junctions can be expected to result in unacceptably high series resistance.
The use of CoSi.sub.2 and TiSi.sub.2 layers in contacts to junctions is known. These layers are conventionally fabricated by a technique that comprises deposition of a thin layer of the metal, followed by an anneal, or that comprises co-deposition of the metal and Si, again followed by an anneal. However, thus produced contacts generally exhibit a rough silicide/Si interface. Consequently, the junctions must typically extend at least about 50 nm beyond the average depth of the silicide layer, in order to avoid high leakage currents and silicide shorting to the substrate. Furthermore, substantially uniform CoSi.sub.2 and TiSi.sub.2 layers less than 50 nm thick are difficult to fabricate by the prior art technique.
In view of the need to have available a technique for contacting ultra-shallow junctions that is not subject to the shortcomings of the prior art, a technique for making relatively low resistance contacts with a substantially uniform metal/semiconductor interface that does not require a high temperature anneal (which can cause unwanted diffusion of dopant) and that is capable of reliably producing metal layers of less than 50 nm thickness, would be of importance. This application discloses such a technique.
R. V. Joshi et al. (Applied Physics Letters, Vol. 54(17), pp. 1672-1674) disclose a contact structure that comprises selectively deposited W on self-aligned TiN/TiSi.sub.2. The silicide layer was formed by deposition of Ti and reaction at 675.degree. C.
U.S. Pat. No. 4,816,421 discloses a method (referred to as "mesotaxy") of making an epitaxial structure that comprises implantation of a metal species (e.g., Co) into a single crystal semiconductor (e.g., Si) body. Under appropriate conditions a buried stoichiometric silicide (e.g., CoSi.sub.2) layer that is epitaxial with the matrix and of good crystalline quality can be formed. Mesotaxy can also produce single crystal CoSi.sub.2 surface layers. However, these layers are invariably more than 50 nm thick. Furthermore, mesotaxy involves implantation at elevated temperature (e.g., 300.degree.-400.degree. C.) and a high temperature (e.g., 900.degree.-1100.degree. C.) anneal, undesirable features in sub-micron CMOS processing.
P. Madakson et al., Journal of Applied Physics, Vol. 62(5), pp. 1688-1693, report on studies of stress and radiation damage in &lt;111&gt; Si after ion implantation with 28 keV Ar.sup.+ and 30 keV Ti.sup.+, with doses ranging from 10.sup.12 to 10.sup.17 ions/cm.sup.2. The effect on stress of annealing at 600.degree. C. was also investigated. For doses above 10.sup.16 Ti.sup.+ /cm.sup.2 and annealing at 600.degree. C. for 2 hours, formation of a Ti-Si layer is reported. The layer reportedly contained both metastable and equilibrium phases, and TiSi.sub.2 precipitates remained in the substrate. See also P. Madakson et al., Material Research Society Symposium Proceedings, Vol. 107, pp. 281-285, which discloses similar results.